The present invention relates to a semiconductor device and method for manufacturing the semiconductor device. More particularly, the invention relates to a semiconductor device which has a multilayer wiring structure and uses a film having a low dielectric constant as an interlayer insulating film and relates to a method for manufacturing the semiconductor device.
As the density of the large scale integration of semiconductor devices has increased, the density of the multilayer wiring structure of the semiconductor devices has also increased. With the increased density of the wiring structure, the wirings adjacent to each other on the same layer and the wirings adjacent to each other on different layers still must be well insulated by an interlayer insulating film.
FIG. 10 shows a sectional view of a semiconductor device having a multilayer wiring structure. Such device is described in Japanese published unexamined patent application No. H8-107149. As shown in the figure, the device contains a semiconductor substrate 101 and an element separating area 102 provided on the semiconductor substrate 101. A diffusion layer area 103 is formed in the semiconductor substrate 101 in an area of the substrate 101 that is partitioned by the element separating area 102.
A metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistor is formed on the diffusion layer area 103 of the semiconductor substrate 101 and contains source and drain areas 121, a gate oxide film 122, a gate electrode 123, and side wall oxide films 124. A first interlayer insulating film 104 is provided over the element separating area 102 and the diffusion layer area 103, and contact openings 105 are selectively formed in the first interlayer insulating film 104. The inner walls of the contact openings 105 are lined with a barrier metal 106, and the contact openings 105 are filled with tungsten 107 which extends to the upper surface of the first interlayer insulating film 104.
Then, a first wiring layer 108 containing mainly aluminum is formed on the first interlayer insulating film 104 at least in an area above the contact openings 105. A first oxide film 109 is formed over the first wiring layer 108 by a plasma chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) process such that the upper and side surfaces of the first wiring layer 108 are covered. Also, the portion of the first oxide film 109 on the side surface of the first wiring layer 108 is thinner than the portion of the first oxide film 109 on the upper surface of the first wiring layer 108. For example, if the portion of the first oxide film 109 on the upper surface has a thickness of 100 nm, the portion of the film 109 on the side surface has a thickness of approximately 50 nm.
Also, a hydrogen silsesquioxane (xe2x80x9cHSQxe2x80x9d) layer 110 is used as a film having a low dielectric constant and is formed over the first oxide film 109, and a second oxide film 111 is formed on the upper surface of the HSQ layer 110. Then, the upper surface of the second oxide film 111 is flattened. Since the portion of the first oxide film 109 on the side surface of the first wiring layer 108 is thin in comparison to the portion of the film 109 on the upper surface, the space in which the HSQ layer 110 (i.e. the film with the low dielectric constant) is provided between the wirings of the first wiring layer 108 is increased. Therefore, the spacing between adjacent wirings can be reduced. Also, instead of using the HSQ layer 110 as the film with a low dielectric constant, a layer of parylene, benzocyclobutene (xe2x80x9cBCBxe2x80x9d), or other material may be used.
A via hole 112 is selectively formed in the first oxide film 109, the HSQ layer 110, and the second oxide film 111, and the inner wall of the via hole 112 is lined with a barrier metal 113 which extends to the upper surface of the second oxide film 111. Then, the via hole 112 is filled with tungsten 114. A second wiring layer 115 containing an aluminum alloy is formed on the second oxide film 111 at least in an area above the via hole 112. A cover film 116 consisting of plasma SiON which is 1 xcexcm thick is formed on the second wiring layer 115.
The method in which the semiconductor device shown in FIG. 10 is manufactured will be described below in conjunction with FIGS. 11A, 11B, and 12. As shown in FIG. 11A, the element separating area 102 is formed on the semiconductor substrate 101 by a LOCOS method and other methods, and the diffusion layer area 103 is formed via ion implantation in an area of the semiconductor substrate 101 defined by the element separating area 102. The source and drain areas 121 are formed in the diffusion layer area 103, and the gate oxide film 122, the gate electrode 123, and the side wall oxide films 124 of the MOS transistor are formed on the diffusion layer area 103.
The first interlayer insulating film 104 is formed over the element separating area 102, the diffusion layer area 103, and the MOS transistor. Also, the first interlayer insulating film 104 contains an oxide film layer which is approximately 100 nm thick and a boron phospho silicate glass (xe2x80x9cBPSGxe2x80x9d) layer which is approximately 700 nm thick and which is formed on the oxide film layer. The contact openings 105 are selectively formed over the source and drain areas 121 of the MOS transistor, and the barrier metal 106 is formed on the inner surface of the contact openings 105. Then, the contact openings 105 are filled with tungsten 107 via a CVD process, and the first wiring layer 108 containing an aluminum alloy is formed over at least the contact openings 105 via a patterning process. The first wiring layer 108 has a thickness of 0.4 xcexcm, and the distance between adjacent wirings of the first wiring layer 108 is approximately 0.3 xcexcm.
As shown in FIG. 11B, the first oxide film 109 is formed over the first interlayer insulating film 104 and the first wiring layer 108 via a plasma CVD process such that it is approximately 50 nm thick on the upper surface of the first wiring layer 108. The HSQ layer 110 is formed by a spin coating method so that it is approximately 400 nm thick in the flat part. In other words, the thickness of the portion of the HSQ layer 110 which is not directly over the wiring layer 108 is approximately 400 nm. Afterwards, the HSQ layer 110 is baked at a temperature of approximately 350xc2x0 C. Then, a heat treatment is applied to the layer 110 at approximately 400xc2x0 C. to eliminate an organic component such as isomethylbutyl ketone which functions as a solvent.
Then, as shown in FIG. 12, the second oxide film 111 is formed over the HSQ layer 110 and is approximately 2 xcexcm thick. Afterwards, the second oxide film 111 is flattened by a chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) process and other processes. The via hole 112 is selectively made through the is first oxide film 109, the HSQ layer 110, and the second oxide film 111, and the barrier metal 113 containing titanium nitride is formed on the inner surface of the via hole 112. Then, the via hole 112 is filled with tungsten 114 formed by a blanket CVD process, and an etchback process is performed. Afterwards, the second wiring layer 115 containing an aluminum alloy is formed via a patterning process and has a thickness of 0.4 xcexcm. Then, the semiconductor device is completed by forming the cover film 116 containing plasma SiON on the second wiring layer 115 at a thickness of approximately 1 xcexcm.
In the semiconductor device described above, the first oxide film 109 formed on the side wall of the first wiring layer 108 is thinned in order to enhance the effect achieved by the HSQ layer 110 having a low dielectric constant. However, since the first oxide film 109 is thinned, moisture in the HSQ layer 110 can penetrate the first oxide layer 109. As a result, the moisture increases the current which leaks between the adjacent wirings of the first wiring layer 108. Also, the moisture creates voids in the wiring layer 108 and decreases the ability of the wirings to withstand electromigration. When electromigration occurs in the wirings of the first wiring layer 108, aluminum atoms in the wirings migrate due to electron flow, and voids are formed in the wirings. As a result, the resistance of the wirings is increased and the speed of the circuit is decreased. The above problems are further exaggerated if the miniaturization of a semiconductor device is increased and the distance between adjacent wirings is reduced. The exaggeration of such problems occurs because the space between the adjacent wirings is reduced. Specifically, in such case, the oxide film 109 on the side wall of the wirings must be further thinned to increase the amount of the HSQ layer 110 that can be disposed between the wirings.
Also, in general, when the via hole 112 is selectively formed, a photoresist (not shown) is used as a mask and is peeled away. Then, an ashing process using an O2 plasma and a wetting process are executed. However, when the wetting process is executed, moisture is absorbed in the portion of the HSQ layer 110 that is exposed to the side wall of the via hole 112. As the absorbed moisture seeps into the via hole 112 when the barrier metal 113 is formed by a sputtering process or during a thermal process after the barrier metal 113 is formed, a cavity is formed in the via hole 112. As a result, the size (i.e. circumference) of the via hole 112 is reduced, and an opening in the via hole 112 may fail to occur. Since the size of the via hole 112 is reduced, its resistance is increased. The chances of the opening not occurring are dramatically increased as the diameter of the via hole 112 is reduced in an attempt to reduce the size of the semiconductor device. The reason that the chances increase is because the ratio of the side area of the HSQ layer 110 containing the moisture to the volume of the via hole 112 increases as the diameter of the via hole 112 is reduced. Furthermore, since the HSQ layer 110 connects a path between adjacent via holes 112, the leak current between the adjacent via holes 112 increases.
In order to attempt to overcome the above problems, the side wall of a via hole can be covered with an inorganic material such as an oxide film as described in Japanese published unexamined patent applications No. H3-209828 and No. H8-139194. However, in the above technique, an insulating film such as an oxide film is deposited in the via hole after the via hole is made, and thus, the effective diameter of the completed via hole is smaller than the initially intended diameter of the via hole. As a result, the resistance in the via hole is increased. Also, the diameter of the via hole cannot be controlled, and thus, resistance in the via hole is not fixed. In order to reduce the resistance in a via hole and remove a natural oxide film on the layer wiring exposed at the bottom of the via hole, a plasma processing method has been proposed in Japanese published unexamined patent application No. H8-046038. However, when a diffusion type plasma source is used to reduce damage caused by ion irradiation during the plasma processing method, the cost of manufacturing the semiconductor device is substantially increased.
An object of the present invention is to prevent leak current between adjacent wirings from increasing when the distance between the wirings is reduced.
Another object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the deterioration of the reliability of the wiring is prevented.
A further object of the present invention is provide a semiconductor device and a method for manufacturing the semiconductor device in which the increase of resistance in a via hole is prevented, the chance that an opening in the via hole will not be created is reduced, the deterioration of the resistance of the via hole to electromigration is prevented, and the leak current via the via hole is prevented.
In order to achieve the above and other objects, a semiconductor device is provided. The device comprises: a substrate; a first wiring layer; a first oxide film formed on said first wiring layer; a dielectric film having a low dielectric constant formed on said first oxide film; a first nitrogen layer containing nitrogen formed in said first oxide film; a second wiring layer, wherein said dielectric film is disposed between said second wiring layer and said first wiring layer; a via hole formed through said dielectric film and disposed between said first wiring layer and said second wiring layer for electrically connecting said first wiring layer and said second wiring layer; a second nitrogen layer containing nitrogen formed on a side wall of said via hole.
In order to further achieve the above and other objects, a method for manufacturing a semiconductor device is provided. The method comprises the steps of: (a) forming a first wiring layer according to a predetermined pattern at least indirectly on a substrate; (b) forming a first oxide film above said first wiring layer; (c) forming a first nitrogen layer in said first oxide film by supplying said first oxide film with nitrogen; (d) forming a dielectric film with a low dielectric constant above said first oxide film; (e) forming a second wiring layer, wherein said dielectric film is disposed between said first wiring layer and said second wiring layer; (f) forming a via hole through said dielectric film to connect said first wiring layer and said second wiring layer; and (g) forming a second nitrogen layer in a side wall of said via hole by supplying said side wall with nitrogen.